Abstract

ALPIZAR-CASTILLO, Joel. Seven levels triphasic inverter design controlled by a state machine. Tecnología en Marcha [online]. 2017, vol.30, n.2, pp.87-96. ISSN 0379-3982.  http://dx.doi.org/10.18845/tm.v30i2.3200.

[16]

This article describes the design of a seven levels triphasic inverter circuit, separated in three stages: monophasic signal generation stage, control stage and offset stage. For the monophasic signal generation stage was used an asymmetric cascade inverter based thyristors. For the control stage was used a finite state machine with JK flip-flops. For the offset stage, monoestable circuit was preferred over an RC circuit, because it causes significant power losses and negative effects on the output signal.

Keywords : Inverter bridge; inverter circuit; offset circuit; power electronics; state machine; triphasic inverter.

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